1. Field of Use
This invention relates to memory systems and more particularly to memory controller apparatus for processing a plurality of memory requests involving transfers of data between memory systems and data processing units over a common bus.
2. Prior Art
It is well known to construct memory systems from a number of memory modules. In certain prior art systems, memory modules are paired together to provide a double word fetch access capability. The term double word fetch access as used herein refers to the capability of being able to access a pair of words at a time from a memory system during a cycle of operation. This type of system is described in U.S. Pat. No. 4,236,203 titled "System Providing Multiple Fetch Bus Cycle Operation", invented by John L. Curley, Robert B. Johnson, Richard A. Lemay and Chester M. Nibby, Jr., issued Nov. 25, 1980 and assigned to the same assignee as named herein.
In the above prior art system, the memory system connects to an asynchronously operated single word wide bus. In the arrangement a request for multiple words is made in a single bus cycle and the requested information words are delivered to the bus over a series of response cycles. While this arrangement improves the system throughput capabilities, it becomes desirable to be able to provide a memory system able to respond to a plurality of requests involving the transfer over a single bus, groups of multiple words accessed simultaneously during a series of cycles without incurring communication delays. This becomes desirable where it is required to provide a high speed transfer of data to another memory device such as a cache unit or disk device.
The system disclosed in the copending patent application "A Memory Controller with Interleaved Queuing Apparatus" referenced above enables such high speed transfers to take place.
The memory controller of the system includes a plurality of queue circuits. Each of the queue circuits includes an address queue register, a control queue register and at least one data queue register. Each address queue register includes tristate control circuits for enabling independent operation in processing memory requests.
Also, the controller includes control circuits which couple to the address, control and data registers of each of the queue circuits. The control circuits operate to assign memory cycles of operation on an alternate basis when the queue control registers store memory requests which are being processed by the queue circuits.
By interleaving the processing of different types of memory requests, the controller is able to process memory requests in parallel. This eliminates processing delays, particularly in the case where one of the types of memory requests being processed requires a multiword transfer over a number of successive memory cycles of operation. That is, one type of request identified as a burst memory request can involve the transfer of a substantial number of data words to the bus over a number of bus cycles of operation. By interleaving memory cycles between the queue circuits, the processing of non-burst memory requests normally requiring a single memory cycle are not delayed.
While the controller arrangement described above eliminates delays in processing nonburst requests, there are certain system arrangements in which lower priority requesting units are unable to gain access to the controller's empty queue circuit. It has been found that this occurs when the nonburst requests generated by the lower priority requesting units are subjected to long delays prior to receipt by the higher priority controller (e.g. the bus propagation time is 300 nanoseconds or greater).
As a result of the above, the bus network to which the units and controller connect becomes saturated, in such system arrangements, and are prevented from carrying out a single burst operation involving multiple word transfers over successive bus cycles of operation. The result of such conflicts in data transfers is that there is a corresponding loss in system processing throughput.
Accordingly, it is a primary object of the present invention to provide a system which is able to process a plurality of memeory requests specifying data transfers between a memory subsystem and a plurality of devices from such devices with a minimum of conflict.
It is a further object of the present invention to provide a system including a memory controller with apparatus for concurrently processing nonburst requests from a plurality of devices in parallel with a burst request involving the transfer of groups of data words over a common bus network during consecutive bus cycles of operation notwithstanding the positioning of such devices on the bus network.